1. Field of the Invention
The invention relates to integrated circuits, and more particularly, to integrated circuits with low power consumption.
2. Description of the Related Art
As power consumption and device reliability are of increasing concern in densely integrated circuits and systems, the supply voltage has been scaled down and is expected to be less than 1V in circuits used in lower power consumption devices such as portable computers, mobile telephones and personal digital assistants (PDAs), for example. Unfortunately, using a lower voltage can result in performance degradation due to reduced |Vgs| and an increase of standby current due to scaled threshold voltages of transistors. Various circuit techniques have been proposed to solve the problems caused by reduced supply voltages in sub-1V region. MOS (metal-oxide-semiconductor) parameters such as the threshold voltages, and the gate and source voltages of transistors have been controlled to achieve the design goals. MOS-threshold-voltage-control techniques include: MTCMOS (Multi-Threshold CMOS), described in S. Mutoh et al, IEEE Journal of Solid State Circuits, 30(8): 845-854, August 1995; VTCMOS (Variable Threshold CMOS), described in T. Kuroda et al, ISSCC Digest of Technical Papers, pages 166-167, February 1996, and K. Seta et al, ISSCC Digest of Technical Papers, pages 166-167, February 1995; and DTMOS (Dynamic Threshold-voltage MOS), described in F. Assaderaghi et al, in International Electron Devices Meeting, Digest of Technical Papers, pages 809-812, June 1994. MOS-gate-voltage-control techniques include: Gate-Over-Driving CMOS described in, T. Iwata et al, in ISSCC Digest of Technical Papers, pages 290-291, February 1997; and SCCMOS(Super Cut-Off CMOS), described in Kawaguchi et al. in ISSCC Digest of Technical Papers, pages 192-193, February 1998. A MOS-source-voltage-control technique includes: Switched-Source-Impedance CMOS, described in M. Horiguchi et al, IEEE Journal of Solid State Circuits, 28(11):1131-1135, November 1993. Even though previous techniques have shown potential solutions they also have drawbacks such as, limitations relating to low supply voltage, complicated data holding schemes and/or an on-chip boost voltage generator, and gate oxide reliability problems, for example.
FIG. 1 is an illustrative circuit diagram showing a basic MTCMOS type circuit. MOS transistors with different threshold voltages Vt are used to improve performance in the active mode while reducing leakage current in standby mode. In particular, low Vt transistors provide rapid switching performance in an active mode, and high Vt transistors serve to reduce subthreshold leakage current in the standby mode. The low Vt transistors shown in FIG. 1 within dashed lines are interconnected as one or more multi-state logic circuits that perform logic functions or data storage functions. Transistor Q1 is a high Vt PMOS transistor, and transistor Q2 is a high Vt NMOS transistor. During active mode, Q1 and Q2 are turned on, and the multi-state logic circuits are active and can perform logical or data storage functions. During standby mode, Q1 and Q2 are turned off, and the multi-state circuits become inactive.
There have been shortcomings with MTCMOS type circuits. For example, it will be appreciated that an MTCMOS circuit has a lower limit of supply voltage due to the presence of higher Vt transistors. In other words, the threshold higher voltage sets a lower limit on the supply voltage level. In general, the higher the threshold voltage is, the higher the lower limit of the supply voltage is. Also, relatively large transistor sizes for Q1 and Q2 may be required to meet performance requirements (e.g. current flow) in the sub-1V region. In addition, since virtual power lines (VDDV and GNDV) float in standby mode, special data holding circuitry such as a balloon circuit may be needed to preserve data safely in a standby mode. An example of a suitable data holding circuit is described in, S. Shigematsu et al, IEEE Journal of Solid State Circuits, 32(6):861-869, June 1997.
Thus, one of the impediments to lower voltage integrated circuits has been increased leakage current in the lower Vt transistors. One earlier approach to reducing leakage current through PMOS transistors (such as a PMOS transistor in the position of Q1 in FIG. 1) without employing a high Vt transistor has been to use an on-chip boost voltage (VPP) for the control signal (SL) and control signal bar (SLB) as in Gate-Over-Driving CMOS and SCCMOS (Super Cut-Off CMOS). In standby mode, since the control signal voltage is VPP-(˜1.5 Vdd). Q1 would be reverse biased, and the leakage current would be suppressed. But these MOS-gate-control methods generally require N-well separation and a highly efficient on-chip boost voltage generator which can be difficult to achieve in sub-1V region. Oxide reliability is another problem. Since logic state information can be lost in standby mode MTCMOS, and SCCMOS may include a flip-flop with a high Vt SRAM cell for data holding in standby mode.
MOS threshold voltages also can be controlled by adjusting the substrate bias voltages as in a VTCMOS, circuit or in a DTMOS circuit. As shown in FIG. 2, for example, different substrate bias voltages can be applied by a self substrate bias generator so as to produce a low threshold voltage in active mode and a high threshold voltage in standby mode. VTCMOS techniques, however, ordinarily require a relatively large supply voltage to change the threshold voltage by a few hundred mV since changes in the threshold voltage generally depend on the square root of the source to substrate voltage. Other problems can arise due to a triple well structure and/or due to additional power lines for well bias and due to slow response time to well bias changes.
As shown in FIG. 3, in DTMOS, threshold voltages are changed dynamically according to an input state. Even though this scheme can possibly lower the supply voltage further, it typically involves silicon-on-insulator (SOI) technology which can suffer from increased leakage current due to inherent forward bias current of pn-junctions as explained by Kawaguchi, et al.
Thus, there as been a need for low power consumption high performance circuits. The present invention meets that need.